In order to increase the number of component MOS-type field effect transistors, the device dimensions must be scaled down, so that many undesirable effects tend to take place in each component MOS-type field effect transistor due to short channel. One of the undesirable effects is known as the injection of hot electrons produced by an extremely large electric field around the drain region. This results in driftage of the threshold voltage. One of approaches to overcome the problem in driftage of the threshold voltage is to provide source/drain regions each formed by two impurity regions different in impurity concentration from each other. The MOS-type field effect transistor thus arranged is capable of reduction of the injection of hot carriers by virtue of the lightly-doped impurity region forming part of each source /drain region. The structure of the MOS-type field effect transistor is called as an LDD-structure.
In FIG. 1 of the drawings, there is shown a typical example of the MOS-type field effect transistor of the type having the source/drain regions each formed by the combination of the two different impurity regions. The MOS-type field effect transistor shown in FIG. 1 is fabricated on a p-type silicon substrate 1 on which a gate insulating film 2 and a gate structure is formed by using usual techniques. The gate structure comprises an gate electrode 3 covered with a thin dielectric film 4 and side walls 5 and 6 provided on both sides of the gate electrode 3. In the p-type silicon substrate 1 are formed source/drain regions each consisting of a lightly doped portion 7 or 8 and a heavily doped portion 9 or 10. The source/drain regions are covered with a thin silicon oxide film 11, so that the side walls 5 and 6 are provided on the thin silicon oxide film 11.
In the fabrication process of the MOS-type field effect transistor, the gate electrode 3 is formed by using lithographic techniques, and phosphorus atoms are lightly implanted into the p-type silicon substrate 1 in a self-aligned manner using the gate electrode 3 as a ask. After formation of the lightly doped portions 7 and 8, polysilicon or silicon dioxide is deposited entire surface of the structure by using a chemical vapor deposition technique to form a polysilicon film or a silicon dioxide film covering the entire surface of the structure. The polysilicon film or the silicon dioxide film is anisotropically etched away until the thin insulating film is exposed, so that the side walls 5 and 6 remain on the thin dielectric film 4 covering both sides of the gate electrode 3. When the side walls 5 and 6 are formed, arsenic atoms are heavily implanted into the p-type silicon substrate using the side walls 5 and 6 as a mask.
The MOS-type field effect transistor thus formed has the lightly doped portions 7 and 8 contiguous to a channel forming area below the gate electrode 3, so that electric fields induced around the source/drain regions are decreased in intensity, thereby reducing the injection of the hot electrons. However, a problem is still encountered in the MOS-type field effect transistor shown in FIG. 1 in driftage of the transistor's characteristics such as, for example, the threshold voltage and the channel conductance. This is because of the fact that the hot electrons are trapped in the dielectric film underneath the side walls 5 and 6 during operation thereof.